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high voltage, isolated gate driver with internal miller clamp, 2 a output data sheet ADUM4121 / ADUM4121 - 1 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no respons ibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under a ny patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2016 ana log devices, inc. all rights reserved. technical support www.analog.com f eatures 2 a peak output current (< 2 r dson ) 2. 5 v to 6 .5 v input 4.5 v t o 3 5 v output undervoltage lockout ( uvlo ) at 2. 5 v v dd1 multiple uvlo option s on v dd2 grade a : 4.4 v (typ ical ) uvlo on v dd2 grade b : 7. 3 v (typ ical ) uvlo on v dd2 grade c : 11. 3 v ( typical ) uvlo on v dd2 precise timing characteristics 5 3 ns maximum isolator and driver p ropagation d elay cmos input logic levels high common - mode transient immunity: > 1 5 0 kv/s high junction temperature operation: 1 2 5c default low output internal miller clamp safety and regulatory approvals (pending) ul recogni tion per ul 1577 5 k v rms for 1 - minute withstand csa component acceptance notic e 5a vde certificate of conformity (pending) din v vde v 0884 - 10 (vde v 0884 - 10): 2006 - 12 v iorm = 849 v peak wide - body, 8 - lead soic a pplications switching power supplies isolated igbt/mosfet gate drives industrial inverters gallium n itride (gan) / silicon carbide (sic) p ower d evices general description the ADUM4121 / ADUM4121 - 1 1 are 2 a isolated, single - channel driver s that employ analog devices , i n c . s i coupler? technology to provide precision isolation . the ADUM4121 / ADUM4121 - 1 provide 5 k v rms isolation in the wide - body , 8 - lead soic package . combining high speed cmos and monolithic transformer technology, th e s e isolation component s provide outstand ing performance characteristics superior to alternatives such as the combination of pulse transformers and gate drivers . the ADUM4121 / ADUM4121 - 1 operate with an input supply ranging from 2. 5 v to 6 .5 v, providing compatibility with lower voltage systems. in comparison to gate drivers that employ high voltage level tra nslation methodologies, the ADUM4121 / ADUM4121 - 1 offer the benefit of true, galvanic isolation between the input and the output . the ADUM4121 / ADUM4121 - 1 include an internal miller clamp that activates at 2 v on the falling edge of the gate drive output, supplying the driven gate with a lower impedance path to reduce the chance of miller capacitance induced turn on. options exists to allow the thermal shutdown to be enabled or disabled . as a result, the ADUM4121 / ADUM4121 - 1 provide reliable control over the switching characteristics of insulated gate bipolar transistor ( igbt ) / metal oxid e semiconductor field, effect transistor (mosfet) c onfigurations over a wide range of switching voltages. functional block dia gram figure 1. 1 protected by u.s. patents 5,952,849; 6,873,065; 7,075,239. other patents pending. encode decode and logic v dd1 v i + gnd 1 v dd2 v out clamp gnd 2 ADUM4121/ ADUM4121-1 uvlo uvlo tsd v i ? 2v 1 2 3 4 8 7 6 5 14967-001
ADUM4121/ADUM4121 - 1 data sheet rev. 0 | page 2 of 16 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general desc ription ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 electrical characteristics ............................................................. 3 regulatory information ............................................................... 4 package characteristics ............................................................... 4 insulation and safety - related specifications ............................ 5 din v vde v 0884 - 10 (vde v 0884 - 10) insulation characteristics .............................................................................. 5 recommended operating conditions ...................................... 5 absolute maximum ratings ............................................................ 6 esd caution ...................................................................................6 pin configuration and function descriptions ..............................7 typical performance characteristics ..............................................8 theory of operation ...................................................................... 11 applications information .............................................................. 12 printed circuit board (pcb) layout ....................................... 12 propagation delay - related parameters ................................... 12 undervoltage lockout ............................................................... 12 output load characteristics ..................................................... 13 power dissipation ....................................................................... 13 insulation lifetime ..................................................................... 14 typical applications ................................................................... 14 outline dimensions ....................................................................... 16 ordering guide .......................................................................... 16 revision history 10/ 20 1 6 revision 0 : initial version
data sheet ADUM4121/ADUM4121 - 1 rev. 0 | page 3 of 16 specifications electrical character istics low - side voltages referenced to gnd 1 . high side voltages referenced to gnd 2 ; 2. 5 v v dd1 6.5 v; 4.5 v v dd2 3 5 v, t j = ?40c to +125c . all minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted. all typical specifications are at t j = 25c, v dd1 = 5.0 v, v d d2 = 15 v. table 1 . parameter symbol min typ max unit test conditions/comments dc specifications high side power supply v dd2 input voltage v dd2 4.5 3 5 v v dd2 input current, quiescent i dd2(q) 2.3 2.7 ma logic supply v dd1 input voltage v dd1 2. 5 6.5 v input current i dd1 3.6 5 ma v i + = h igh, v i ? = l ow logic inputs ( v i + , v i ? ) input current i i + , i i ? ? 1 0.01 + 1 a input voltage logic high v ih 0.7 v dd1 v 2. 5 v v dd1 5 v 3.5 v v dd1 > 5 v logic low v il 0.3 v dd1 v 2. 5 v v dd1 5 v 1.5 v v dd1 > 5 v uvlo v dd1 positive - going threshold v vdd1uv+ 2. 45 2. 5 v negative - going threshold v vdd1uv ? 2.3 2.35 v hysteresis v vdd1uvh 0. 1 v v dd2 grade a positive going threshold v vdd2uv+ 4.4 4.5 v negative going threshold v vdd2uv? 4.1 4.2 v hysteresis v vdd2uvh 0.2 v grade b positive going threshold v vdd2uv+ 7.3 7.5 v negative going threshold v vdd2uv? 6.9 7.1 v hysteresis v vdd2uvh 0.2 v grade c positive going threshold v vdd2uv+ 11.3 11. 6 v negative going threshold v vdd2uv? 10.8 11.1 v hysteresis v vdd2uvh 0.2 v thermal shutdown (tsd) the ADUM4121 - 1 does not have tsd positive edge t tsd_pos 155 c hysteresis t tsd_hyst 30 c internal nmos gate resistance r dson_n 0.6 1.6 tested at 250 ma, v dd2 = 15 v 0.6 1.6 tested at 1 a , v dd2 = 15 v internal pmos gate resistance r dson_p 0.8 1.8 tested at 250 ma, v dd2 = 15 v 0.8 1.8 tested at 1 a , v dd2 = 15 v internal miller clamp resistance r dson_miller 0.8 2 tested at 200 ma, v dd2 = 15 v miller clamp voltage threshold v clp_th 1.75 2 2.25 v referenced to gnd 2 , v dd2 = 15 v peak current i pk 2.3 a v dd2 = 12 v, 4 gate resistance switching specifications pulse width pw 50 ns c l = 2 nf, v dd2 = 15 v, r gon 1 = r goff 1 = 5 propagation delay rising edge 2 t dlh 22 32 42 ns c l = 2 nf, v dd2 = 15 v, r gon = r goff = 5 falling edge 2 t dhl 30 38 53 ns c l = 2 nf, v dd2 = 15 v, r gon = r goff = 5
ADUM4121/ADUM4121 - 1 data sheet rev. 0 | page 4 of 16 parameter symbol min typ max unit test conditions/comments skew 3 t psk 22 ns c l = 2 nf, v dd2 = 15 v, r gon = r goff = 5 falling edge 4 t pskhl 12 ns c l = 2 nf, v dd2 = 15 v, r gon = r goff = 5 rising edge 5 t psk lh 15 ns c l = 2 nf, v dd2 = 15 v, r gon = r goff = 5 pulse width distortion t pwd 7 13 ns c l = 2 nf, v dd2 = 15 v, r gon = r goff = 5 output rise/fall time (10% to 90%) t r /t f 11 18 26 ns c l = 2 nf, v dd2 = 15 v, r gon = r goff = 5 common - mode transient immunity (cmti) |cm| static cmti 6 150 kv/s v cm = 1500 v dynamic cmti 7 150 kv/s v cm = 1500 v 1 r gon and r goff are the external gate resistors in the test. 2 t dlh propagation delay is measured from the time of the input rising logic high threshold, v ih , to the output rising 10% threshold of the v out signal. t dhl pr opagation delay is measured from the input falling logic low threshold, v il , to the output falling 90% threshold of the v ox signal. s ee figure 24 for waveforms of the propagation delay parameters. 3 t psk is the magnitude of the worst case difference in t dlh and/or t dhl tha t is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. see figure 24 f or waveforms of the propagation delay parameters. 4 t pskhl is the magnitude of the worst case difference in t dhl that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions . see figure 24 for waveforms of the propagation delay parameters. 5 t psklh is the magnitude of the worst case difference in t dlh that is measured bet ween units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. see figure 24 for waveforms of the propagation delay parameters. 6 static common - mode transient immunity (cmti) is defined as the largest dv/dt between gnd 1 and gnd 2 , with inputs held either high or low, such that the output voltage remains either above 0.8 v dd2 for output high or 0.8 v for output low. operation with transients above recommended levels can cause momentary data upsets. 7 dynamic common - mode transient immunity (cmti) is defined as the largest dv/dt between gnd 1 and gnd 2 with t he switching edge coin cident with the transient test pulse. operation with transients above the recommended levels can cause momentary data upsets. regulatory informati on the ADUM4121 / ADUM4121 - 1 are pend ing approval by the organizations listed in table 2 . table 2 . ul (pending) csa (pending) vde (pending) cqc (pending) ul1577 component recognition program approved under csa component acceptance notice 5a din v vde v 0884 - 10 (vde v 0884 - 10):2006 - 12 certified under cqc11 - 471543 - 2012 single protection, 5000 v rms isolation voltage csa 60950 - 1 - 07+a1+a2 and iec 60950 - 1, second edition, +a1+a2: reinforced insulation, 849 v peak, v iosm = 10 kv peak gb4943.1 - 2011 basic insulation at 800 v rms (1131 v peak) basic insulation 849 v peak, v iosm = 16 kv peak basic insulation at 800 v rms (1131 v peak) reinforced insulation at 400 v rms (565 v peak) reinforced insulation at 400 v rms (565 v peak) iec 60601 - 1 edition 3.1: basic insulation (1 mopp), 500 v rms (707 v peak) reinforced insulation (2 mopp), 250 v rms (1414 v peak) csa 61010 - 1 - 12 and iec 61010 - 1 third edition basic insulation at: 6 00 v rms m ains, 800 v se c ondary (1089 v peak) reinforced insulation at: 300 v rms m ains, 400 v se c ondary (565 v peak) file e214100 file 205078 file 2471900 - 4880 - 0001 file (pending) package characterist ics table 3 . parameter symbol min typ max unit test conditions/comments resistance (input side to high - side output) 1 r i - o 10 12 capacitance (input side to high - side output) 1 c i - o 2.0 pf input capacitance c i 4.0 pf junction to top characterization parameter jt 7.3 c/w 4 - layer pcb 1 the device is considered a two - terminal device: pin 1 through pin 4 are shorted together, and pin 5 through pin 8 are shorted t ogether.
data sheet ADUM4121/ADUM4121 - 1 rev. 0 | page 5 of 16 i nsulation and safety - related specificatio ns table 4 . parameter symbol value unit conditions rated dielectric insulation voltage 5000 v rms 1 - minute duration minimum external air gap (clearance) l(i01) 8 min mm measured from input terminals to output terminals, shortest distance through air minimum external tracking (creepage) l(i02) 8 min mm measured from input terminals to output terminals, shortest distance path along body minimum clearance in the plane of the printed circuit board (pcb clearance) l (pcb) 8.3 min mm measured from input terminals to output terminals, shortest distance through air, line of sight, in the pcb mounting plane minimum internal gap (internal clearance) 25.5 min m minimum distance through insulation tracking resistance (comparative tracking index) cti > 400 v din iec 112/vde 0303 part 3 isolation group ii material group (din vde 0110, 1/89, table 1) din v vde v 0884 - 10 (vde v 0884 - 10) insulation character istics this isolator is suitable for reinforced isolation only within the safety limit data. maintenance of the safety data is ensur ed by protective circuits. table 5 . vde characteristics description test conditions/comments symbol characteristic unit installation classification per din vde 0110 for rated mains voltage 60 0 v rms i to iv climatic classification 40/105/21 pollution degree per din vde 0110, table 1 2 maximum working insulation voltage v iorm 849 v peak input to output test voltage, method b1 v iorm 1.875 = v pd (m) , 100% production test, t ini = t m = 1 sec, partial discharge < 5 pc v pd (m) 1592 v peak input to output test voltage, method a after environmental tests subgroup 1 v iorm 1.5 = v pd (m) , t ini = 60 sec, t m = 10 sec, partial discharge < 5 pc v pd (m) 1274 v peak after input and/or safety test subgroup 2 and subgroup 3 v iorm 1.2 = v pd (m) , t ini = 60 sec, t m = 10 sec, partial discharge < 5 pc v pd (m) 1019 v peak highest allowable overvoltage v iotm 7000 v peak surge isolation voltage basic vpeak = 16 kv, 1.2 s rise time, 50 s, 50% fall time v iosm 16, 000 v peak surge isolation voltage reinforced vpeak = 16 kv, 1.2 s rise time, 50 s, 50% fall time v iosm 10, 000 v peak safety limiting values maximum value allowed in the event of a failure (see figure 2 ) maximum junction temperature t s 150 c safety total dissipated power p s 1.2 w insulation resistance at t s v io = 500 v r s >10 9 figure 2. thermal derating curve, dependence of safety limiting values on case temperature, per din v vde v 0884 - 10 recommended operatin g conditions table 6 . parameter value operating temperature range (t j ) ?40c to +125c supply voltages v dd1 to gnd 1 2. 5 v to 6.5 v v dd2 to gnd 2 4.5 v to 35 v 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 50 100 150 200 safe limiting power (w) ambient temperature (c) 14967-002
ADUM4121/ADUM4121 - 1 data sheet rev. 0 | page 6 of 16 absolute maximum rat ings ambient temperature = 25c, unless otherwise noted. table 7 . parameter rating storage temperature range (t st ) ?55c to +150c junction operating temperature range (t j ) ?40c to +125c supply voltages v dd1 to gnd 1 ? 0.3 v to + 7 v v dd2 to gnd 2 ? 0.3 v to + 40 v input voltages v i + , v i ? 1 ? 0.3 v to + 7 v v c lamp 2 ? 0.3 v to v dd2 + 0.3 v output voltages v out 2 ?0.3 v to v dd2 + 0.3 v common - mode transients (|cm|) 3 ? 20 0 kv/s to +20 0 kv/s 1 rating assumes v dd1 is above 2.5 v. v i + and v i ? are rated u p to 6.5 v when v dd1 is unpowered. 2 referenced to gnd 2 , maximum of 40 v. 3 |cm| refers to common - mode transients across the insulation barrier. common - mode transients exceeding the absolute maximum rating can cause latch - up or permanent damage. stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or a ny other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. thermal resistance thermal performance is directly linked to printed circuit board (pcb) design and operating environment. careful attention to pcb thermal design is required. ja is thermal resistance, junction to ambient ( c/w ). table 8 . thermal res istance package type ja unit ri - 8 - 1 1 104.2 c/w 1 test condition 1: thermal impedance simulated values are based on a 4 - layer pcb . esd caution table 9 . maximum continuous working voltage 1 parameter rating unit constraint ac voltage bipolar waveform basic insulation 849 v peak 50 - year minimum insulation lifetime reinforced insulation 789 v peak lifetime limited by package creepage maximum approved working voltage per iec 60950 -1 unipolar waveform basic insulation 1698 v peak 50 - year minimum insulation lifetime reinforced insulation 849 v peak 50 - year minimum insulation lifetime dc voltage basic insulation 1118 v peak lifetime limited by package creepage maximum approved working voltage per iec 60950 -1 reinforced insulation 558 v peak lifetime limited by package creepage maximum approved working voltage per iec 60950 -1 1 maximum continuous working voltage r efers to continuous voltage magnitude imposed across the isolation barrier. see the insulation lifetime section for more details. table 10 . truth table v i ? v i + v dd1 state v dd2 state v out output dont care low powered powered low low high powered powered high high dont care powered powered low dont care dont care unpowered powered low dont care dont care powered unpowered low 1 1 the o utput is low, but not actively driven because the device is not powered.
data sheet ADUM4121/ADUM4121-1 rev. 0 | page 7 of 16 pin configuration and fu nction descriptions figure 3. pin configuration table 11. pin function descriptions pin no. mnemonic description 1 v dd1 supply voltage for isolator side 1. 2 v i + noninverting gate drive logic input. 3 v i ? inverting gate drive logic input. 4 gnd 1 ground 1. this pin is the ground reference for isolator side 1. 5 gnd 2 ground 2. this pin is the ground reference for isolator side 2. 6 clamp miller clamp and gate voltage sense. connect this pin directly to the gate being driven. 7 v out gate drive output. connect this pin to the gate be ing driven through an external series resistor. 8 v dd2 supply voltage for isolator side 2. 1 2 3 4 8 7 6 5 ADUM4121/ ADUM4121-1 top view (not to scale) v dd1 v i + gnd 1 v i ? v dd2 v out clamp gnd 2 14967-003
ADUM4121/ADUM4121-1 data sheet rev. 0| page 8 of 16 typical performance characteristics figure 4. v i + to v gate waveform for 2 nf load, 3.9 series gate resistor, v dd2 = 15 v (v gate is the voltage after a gate resistor) figure 5. v i ? to v gate waveform for 2 nf load, 3.9 series gate resistor, v dd2 = 15 v figure 6. v i + to v gate waveform for 2 nf load, 0 series gate resistor, v dd2 = 15 v figure 7. v i ? to v gate waveform for 2 nf load, 0 series gate resistor, v dd2 = 15 v figure 8. typical v dd1 delay to output waveform, v i + = v dd1 , v i ? = gnd 1 figure 9. i dd2 vs. duty cycle, v dd1 = 5 v, switching frequency (f sw ) = 10 khz, 2 nf load ch1 2.0v/div ch2 5.0v/div b w : 1.0g b w : 1.0g a ch1 840mv 40.0ns/div 5.0gs/s 200ps/pt 1 2 v i + v gate 14967-101 ch1 2.0v/div ch2 5.0v/div b w : 1.0g b w : 1.0g a ch1 840mv 40.0ns/div 5.0gs/s 200ps/pt 1 2 v i ? v gate 14967-102 ch1 2.0v/div ch2 5.0v/div b w : 1.0g b w : 1.0g a ch1 840mv 40.0ns/div 5.0gs/s 200ps/pt 1 2 v gate v i + 14967-103 ch1 2.0v/div ch2 5.0v/div b w : 1.0g b w : 1.0g a ch1 840mv 40.0ns/div 5.0gs/s 200ps/pt 1 2 v gate v i ? 14967-104 ch1 2.0v/div ch2 5.0v/div b w : 1.0g b w : 1.0g a ch1 840mv 2.0s/div 5.0gs/s 200ps/pt 1 2 v out v dd1 14967-105 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 20406080100 i dd2 (ma) duty cycle (%) v dd2 = 15v v dd2 = 10v v dd2 = 5v 14967-106
data sheet ADUM4121/ADUM4121-1 rev. 0 | page 9 of 16 figure 10. i dd1 vs. duty cycle, f sw = 10 khz, 2 nf load figure 11. i dd1 vs. frequency figure 12. i dd2 vs. frequency with 2 nf load figure 13. propagation delay vs. v dd1 , v dd2 = 15 v, 2 nf load, 0 gate resistor figure 14. propagation delay vs. temperature, 2 nf load figure 15. propagation delay vs. v dd2 , 2 nf load 0 1 2 4 6 7 3 5 i dd1 (ma) 0 20406080100 duty cycle (%) v dd1 = 5.0v v dd1 = 3.3v 14967-107 3.0 2.5 2.0 1.5 1.0 0.5 0 0 50 100 150 200 250 300 350 400 450 500 i dd1 (ma) frequency (khz) v dd1 = 5.0v v dd1 = 3.3v 14967-109 5.0 0 i dd2 (ma) 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0 50 100 150 200 250 300 350 400 450 500 frequency (khz) v dd2 = 15v v dd2 = 10v v dd2 = 5v 14967-110 60 50 30 40 10 20 0 2.53.03.54.04.55.05.5 propagation delay (ns) v dd1 (v) t dhl t dlh 14967-108 60 50 40 30 20 10 0 ?40 ?20 0 20 40 60 80 100 120 propagation delay (ns) temperature (c) t dhl t dlh 14967-111 60 50 30 40 10 20 0 5 101520253035 propagation delay (ns) v dd2 (v) t dhl t dlh 14967-114
ADUM4121/ADUM4121 - 1 data sheet rev. 0 | page 10 of 16 figure 16 . rise and fall time vs. v dd2 , 2 nf load, 3.9 resistor figure 17 . peak output current vs. v dd2 , 2 series resistance figure 18 . typical output resistance (r dson ) vs. v dd2 figure 19 . typical output resistance (r dson ) vs. temperature, v dd2 = 1 5 v 40 0 10 5 15 25 35 20 30 4.5 9.5 13.5 24.5 19.5 34.5 29.5 rise/fall time (ns) v dd2 (v) t f t r 14967- 1 15 9 8 7 5 6 3 4 1 2 0 4.5 9.5 14.5 19.5 24.5 34.5 29.5 v dd2 (v) peak output current (a) source current sink current 14967- 1 16 0.9 0.8 0.7 0.5 0.6 0.3 0.4 0.1 0.2 0 4.5 9.0 13.5 18.0 22.5 31.5 27.0 v dd2 (v) r dson () pmos nmos 14967- 1 13 1.2 0 0.2 0.6 1.0 0.4 0.8 ?40 10 60 110 r dson () temperature (c) pmos nmos 14967- 1 12
data sheet ADUM4121/ADUM4121 - 1 rev. 0 | page 11 of 16 theory of operation gate drivers are required in situations where fast rise times of switching device gates are desired. the gate signal for most enhancement type power devices are referenced to a source or emitter node. the gate driver must be able to follow this source or e mitter node, necessitating isolation between the controlling signal and the output of the gate driver in topologies where the source or emitter nodes swing , such as a half bridge. gate switching times are a function of drive strength of the gate driver. bu ffer stages before a cmos output reduce total delay time and increase the final drive strength of the driver. the ADUM4121 / ADUM4121 - 1 achieve isolation between the control side and output side of the gate driver by means of a high frequency carrier that transmits data across the isolation barrier using i coupler chip scale transformer coils separated by layers of polyimide isolation. the encoding scheme used by the ADUM4121 / ADUM4121 - 1 is a positive logic on / off keying (ook) , me aning a high signal is transmitted by the presence of the carrier frequency across the i coupler chip scale transformer coils . positive logic encoding ensures that a low signal is seen on the output when the input side of the gate driver is unpowered. a low state is the most common safe state in enhancement mode power device s, driving in situations where shoot through conditions can exist. the arc hitecture is designed for high common - mode transient immunity and high immunity to electrical noise and magnetic interference. radiated emissions are minimized with a spread spectrum ook carrier and other techniques such as differential coil layout . figure 20 ill ustrates the encoding used by the ADUM4121 / ADUM4121 - 1 . figure 20 . operational block diagram of ook e ncoding transmitter gnd 1 gnd 2 v in v out receiver regul a t or regul a t or 14967-014
ADUM4121/ADUM4121 - 1 data sheet rev. 0 | page 12 of 16 application s i nformation p rinted c ircuit board (pcb) layout the ADUM4121 / ADUM4121 - 1 digital isolator s require no external interface circuitry for the logic interfaces. power supply bypassing is required at the input and output supply pins, as shown in figure 21 . use a small ceramic capacitor with a value between 0.01 f and 0.1 f to provide a good high frequency bypass. on the output power supply pin, v dd2 , it is recommended to also add a 10 f capacito r to provid e the charge required to drive the gate capacitance at the ADUM4121 / ADUM4121 - 1 outputs. on the output supply pin, the bypass capacitor use of vias must be avoided or multiple vias must be employed to r educe the inductance in the bypassing. the total lead length between both ends of the smaller capacitor and the input or output power supply pin must not exceed 20 mm. figure 21 . recommended pcb layout v i + and v i ? operation the ADUM4121 / ADUM4121 - 1 ha ve two d rive inputs, v i + and v i ? , to control the igbt gate drive signals, v out . both the v i + and v i ? pins u se cmos logic level inputs. control t he input logic of the v i + and v i ? pins by either asserting the v i + pin high, or the v i ? pin low. with the v i ? pin low, the v i + pin accepts positive logic. if v i + is held high, the v i ? pin accepts negative logic. figure 22 . v i + and v i ? b lock d iagram see figure 23 for more details. figure 23 . v i + and v i ? t iming diagram propagation delay - related parameters propagation delay is a parameter that describes the t ime a logic signal takes t o propagate through a component. the propagation del ay to a logic low output can differ from the propagation delay to a logic high output. the ADUM4121 / ADUM4121 - 1 specif y t dlh (see figure 24 ) as the time between the rising input hi gh logic threshold, v ih , to the output rising 10% threshold. likewise, the falling propagati on delay, t dhl , is defined as the tim e between the input falling logic low threshold, v il , and the output falling 90% threshold. the rise and fall times are dependent on the loading conditions and are not included in the propagation delay, as is the industry standard for gate drivers. figure 24 . propagation delay parameters channel to channel matching refers to the maximum amount that the propagation delay differs between channels within a single ADUM4121 / ADUM4121 - 1 component. propagation delay s kew refers to the maximum amount that the propagation delay differs between multiple ADUM4121 / ADUM4121 - 1 components operating under the same conditions. under v oltage l ockout (uvlo) the ADUM4121 / ADUM4121 - 1 have uvlo protections for both the primary and secon dary side of the device . if either the primary or secondary side voltages are below the falling edge uvlo, the device out put s a low signal. after t he ADUM4121 / ADUM4121 - 1 are powered above the rising edge uvlo threshold, t he device output s the signal found at the input. hysteresis is built in to the uvlo to account for small voltage source r ipple. the primary side uvlo t hresholds are common among all models. there are three options for the secondary output uvlo t hresholds, listed in table 12 . table 12 . list of model options model number tsd u vlo (v) ADUM4121ariz yes 4.5 ADUM4121briz yes 7. 5 ADUM4121criz yes 11. 6 ADUM4121ariz -1 no 4.5 ADUM4121briz -1 no 7. 5 ADUM4121criz -1 no 11. 6 v dd1 gnd 1 v dd2 gnd 2 v i + v out clamp v i ? 14967-015 v i + v out v i ? 14967-016 v i + v i ? v gate t dhl t dlh 14967-017 output input t dlh t r 90% 10% v ih v il t f t dhl 14967-018
data sheet ADUM4121/ADUM4121 - 1 rev. 0 | page 13 of 16 output load characte ristics the ADUM4121 / ADUM4121 - 1 outp ut signals depend on the characteristics of the output load, which is typically an n channel mosfet. model t he driver output response to an n channel mosfet load with a switch output resistance (r sw ), an inductance due to the printed circuit board trace (l trace ), a series gate resistor (r gate ), a nd a gate to source capacitance (c gs ), as shown in figure 25. r sw is the switch resistance of the internal ADUM4121 / ADUM4121 - 1 driver output, which is about 1.5 ?. r gate is the intrinsic gate resis - tance of the mosfet or igbt and any external series resistance. a mosfet or igbt that requires a 2 a gate driver has a typical intrinsic gate resistance of about 1 ? and a gate to source capa ci - tance, c gs , of between 2 nf and 10 nf. l trace is the inductance of the printed circuit board trace, typically a value of 5 nh or less for a well designed layout with a very short and wide conne ction from the ADUM4121 / ADUM4121 - 1 output to the gate of the mosfet or ig bt . the following equation defines the quality factor, q , of the rlc circuit, which indicates how the ADUM4121 / ADUM4121 - 1 output responds to a step change. for a well damped output, q is less than one . adding a series gate resistance dampens the output response. gs trace gate sw c l r r q + = ) ( 1 output ringing is reduced by adding a series gate resistance to dampen t he response. the waveforms show n in fig ure 4 show a correctly damped example with a 2 nf load and a 3.9 external series gate resistor. the waveforms shown in figure 6 show an underdamped example with a 2 nf load and a 0 external series gate resistor. figure 25 . rlc model of the gate of an n channel mosfet miller clamp the ADUM4121 / ADUM4121 - 1 ha ve an integrated miller clamp to reduce voltage spikes on the mosfet or ig bt gate caused by the miller capacitance during shut off of the mosfet or igbt . when the input gate signal requests the igbt to be turned off (driven low), the miller clamp mosfet is off initially . after the voltage on the g ate s ense pin crosses the 2 v internal voltage reference that is reference d to gnd 2 , the internal miller clamp latches on for the remainder of the off time of the mosfet or i gbt , creating a second low impedance current path for the gate current to follow. the miller clamp switch remain s on until the input drive signal changes from low to high. an example waveform of the timings is shown in figure 26. figure 26 . miller clamp example power dissipation during the driving of a mosfet or igbt gate, the driver must dissipate power. t his power is not insignificant, and can lead to thermal shutdown (tsd) if considerations are not made. the gate of an igbt can be approximately simulated as a capacitive load. due to miller capacitance and other nonlinearities, it is common practice to tak e the stated input capacitance of a given mosfet or igbt , c iss , and multiply it by a factor of 3 to 5 to arrive at a conservative estimate of the approximate load being driven. with this value, the estimated to tal power dissipation in the system due to swi tching action is given by p diss = c est ( v dd2 ? gnd 2 ) 2 f s w w here: c est = c iss 5 . f s w is the switching frequency of the ig bt. alternately, the gate charge can be used as follows: p diss = q g ( v dd2 ? gnd 2 ) f s w w here q g is the total gate charge of the device being driven. this power dissipation is shared between the internal on resistances of the internal gate driver switches, and the external gate resistance s, r gon and r goff . the ratio of the internal gate resist ances t o the total series resistance allows the calculation of losses seen within the ADUM4121 / ADUM4121 - 1 devices . t he following calculations for the ADUM4121 also appl y to the ADUM4121 - 1 . p diss _ ADUM4121 = p diss 0.5 ( r dson_p /( r gon + r dson_p ) + 0.5 ( r dson_n /( r goff + r dson_n )) taking this power dissipation found inside the chip, and multiply - in g i t by the ja gives the rise above ambient temperature that the ADUM4121 expe rience s. t adum41 21 = ja p diss _ADUM4121 + t amb for the device to remain within specification , t ADUM4121 must not exceed 125 c. if t ADUM4121 exceeds the tsd rising edge, the devic e e nter s tsd, and the output remain s low until the tsd falling edge is crossed. the ADUM4121 - 1 does not include thermal shutdown. ADUM4121/ ADUM4121-1 v i v out r sw r gate c gs l trace v o 14967-019 v clamp v dd2 gnd 2 miller clamp switch 2v v i + v i ? on off off latch off latch on 14967-020
ADUM4121/ADUM4121-1 data sheet rev. 0| page 14 of 16 insulation lifetime all insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. the rate of insu- lation degradation is dependent on the characteristics of the voltage waveform applied across the insulation. in addition to the testing performed by the regulatory agencies, analog devices carries out an extensive set of evaluations to determine the lifetime of the insulation structure within the ADUM4121/ ADUM4121-1 . analog devices performs accelerated life testing using voltage levels higher than the rated continuous working voltage. accel- eration factors for several operating conditions are determined. these factors allow calculation of the time to failure at the actual working voltage. the values shown in table 9 summarize the peak voltage for 50 years of service life for a bipolar ac operating condition, and the maximum csa/vde approved working voltages. in many cases, the approved working voltage is higher than the 50-year service life voltage. operation at these high working voltages can lead to shortened insulation life in some cases. the insulation lifetime of the ADUM4121/ ADUM4121-1 depends on the voltage waveform type imposed across the isolation barrier. the i coupler insulation structure degrades at different rates depending on whether the waveform is bipolar ac, unipolar ac, or dc. figure 27, figure 28, and figure 29 illustrate these different isolation voltage waveforms. a bipolar ac voltage environment is the worst case for the i coupler products and is the 50-year operating lifetime that analog devices recommends for maximum working voltage. in the case of unipolar ac or dc voltage, the stress on the insulation is significantly lower. this unipolar ac or dc voltage operation allows operation at higher working voltages while still achieving a 50-year service life. any cross insulation voltage waveform that does not conform to figure 28 or figure 29 must be treated as a bipolar ac waveform, and its peak voltage must be limited to the 50-year lifetime voltage value listed in table 9. note that the voltage presented in figure 28 is shown as sinu- soidal for illustration purposes only. it is meant to represent any voltage waveform varying between 0 v and some limiting value. the limiting value can be positive or negative, but the voltage cannot cross 0 v. figure 27. bipolar ac waveform figure 28. unipolar ac waveform figure 29. dc waveform typical applications a typical application of the ADUM4121 / ADUM4121-1 is shown in figure 30. an external gate resistor, r g , controls the rise and fall times of the gate voltage seen at the device being driven. an optional turn off path is available for further tuning by creating a parallel path through d1. an example bootstrap setup is shown in figure 31. in both of these examples, the v i ? pins are tied low, creating a positive logic input to the gate drivers. in this manner, the v i ? pins act as a disable pin, bringing the outputs low if the v i ? pins are brought high. figure 30. typical application diagram, single device 0v rated peak voltage 14967-023 0v rated peak voltage 14967-024 0v rated peak voltage 14967-025 3 1 2 4 8 7 6 5 ADUM4121/ ADUM4121-1 v i ? v dd1 v i + gnd 1 v dd2 v out clamp gnd 2 r g 0.1f 10f 0.1f gnd 2 d1 v dd2 v dd1 optional r goff 14967-120 notes 1. individual grounds are isolated from each other.
data sheet ADUM4121/ADUM4121-1 rev. 0 | page 15 of 16 figure 31. typical application diagram, bootstrap setup 14967-121 3 1 2 4 8 7 6 5 ADUM4121/ ADUM4121-1 v i ? v dd1 v i + gnd 1 v dd2 v out clamp gnd 2 r ga 0.1f 10f 0.1f d2 d boot optional r gaoff 3 1 2 4 8 7 6 5 ADUM4121/ ADUM4121-1 v i ? v dd1 v i + gnd 1 v dd2 v out clamp gnd 2 r gb 0.1f 20f 0.1f d1 v dd2 v dd1 optional r gboff to load v bus r boot notes 1. individual grounds are isolated from each other.
ADUM4121/ADUM4121 - 1 data sheet rev. 0 | page 16 of 16 outline dimensions figure 32 . 8- lead standard small outline package, with increased creepage [soic_ic] wide body (ri - 8 - 1) dimensions shown in millimeters ordering guide model 1 no. of channels output peak current (a) thermal shutdown minimum output voltage (v) temperature range package description package option ADUM4121ar i z 1 2 yes 4.5 ?40c to +125c 8 - lead soic _ic ri - 8 - 1 ADUM4121ariz -rl 1 2 yes 4.5 ?40c to +125c 8 - lead soic_ic , 13 tape and reel ri -8 -1 ADUM4121briz 1 2 yes 7. 5 ?40c to +125c 8 - lead soic_ic ri -8 -1 ADUM4121briz -rl 1 2 yes 7. 5 ?40c to +125c 8 - lead soic_ic , 13 tape and reel ri -8 -1 ADUM4121 c r i z 1 2 yes 11. 6 ?40c to +125c 8 - lead soic_ic ri -8 -1 ADUM4121criz -rl 1 2 yes 11. 6 ?40c to +125c 8 - lead soic_ic, 13 tape and reel ri -8 -1 ADUM4121 - 1ariz 1 2 no 4.5 ?40c to +125c 8 - lead soic_ic ri -8 -1 ADUM4121 - 1ariz -rl 1 2 no 4.5 ?40c to +125c 8 - lead soic_ic, 13 tape and reel ri -8 -1 ADUM4121 - 1briz 1 2 no 7.5 ?40c to +125c 8 - lead soic_ic ri -8 -1 ADUM4121 - 1briz -rl 1 2 no 7.5 ?40c to +125c 8 - lead soic_ic, 13 tape and reel ri -8 -1 ADUM4121 - 1criz 1 2 no 11. 6 ?40c to +125c 8 - lead soic_ic ri -8 -1 ADUM4121 - 1criz -rl 1 2 no 11. 6 ?40c to +125c 8 - lead soic_ic, 13 tape and reel ri -8 -1 eval - ADUM4121ebz 1 2 yes 4.5 ?40c to +125c evaluation board ri -8 -1 eval - ADUM4121 - 1ebz 1 2 no 4.5 ?40c to +125c evaluation board ri -8 -1 1 z = rohs compliant part. 09-17-2014-b 8 5 4 1 se a ting plane coplanarit y 0.10 1.27 bsc 1.04 bsc 6.05 5.85 5.65 7.60 7.50 7.40 2.65 2.50 2.35 0.75 0.58 0.40 0.30 0.20 0.10 2.45 2.35 2.25 10.51 10.31 10. 1 1 0.51 0.41 0.31 pin 1 mark 8 0 0.33 0.27 0.20 0.75 0.50 0.25 45 ? 2016 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d14967 - 0 - 10/16(0)

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